Testing of Copper Pillar Bumps for Wafer Sort


Tunaboylu B.

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, vol.2, no.6, pp.985-993, 2012 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 2 Issue: 6
  • Publication Date: 2012
  • Doi Number: 10.1109/tcpmt.2011.2173493
  • Title of Journal : IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY
  • Page Numbers: pp.985-993

Abstract

Using a copper pillar interconnect in flip chip packaging provides a lead-free solution that is more reliable, and also scalable to very fine pitch. Vertical probe card technology, also called buckling beam technology, was used in characterization of wafer probe process and electrical contact on solder bumps and copper pillars at 150 mu m pitch arrays. Probe contact was investigated by modeling the scrub, penetration or deformation on a bump under various conditions of wafer probe and experimentally tested on wafers on copper pillars, solder bumps of different metallurgies or sheet wafers. A single-probe contact test system was devised to study the contact behavior of a probe on a bump. Various probe tip geometries including wedge, pointed and flat, were studied. Probing procedures were investigated for achieving reliable electrical contact for large pitch area array bumps as well as fine pitch, 50 mu m, copper pillar array bumps using two different wafer test technologies.