A dynamically reconfigurable communication architecture for multicore embedded systems


JOURNAL OF SYSTEMS ARCHITECTURE, vol.58, pp.140-159, 2012 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 58
  • Publication Date: 2012
  • Doi Number: 10.1016/j.sysarc.2012.02.003
  • Page Numbers: pp.140-159


To deal with the communication bottleneck of multiprocessor systems, several communication architectures have been proposed in the last decade. Yet, none of them has demonstrated the performance of the direct connections between two communicating units. In this paper, we propose dynamically reconfigurable point-to-point (DRP2P) interconnects for setting up direct connection between two communicating units before the communication starts. DRP2P is neither point-to-point (P2P) nor Network-on-Chip (NoC); it stands between these two on-chip communication architectures. It is as fast as P2P and as scalable as NoC. Instead of using routers like in NoC, we utilize partial reconfiguration ability of FPGAs for routing data packets. Furthermore, DRP2P can work both on regular and irregular topologies. The only drawback of our approach is the reconfiguration latency. This drawback is completely hidden when the reconfiguration of the communication links is achieved during the computation times of the cores. DRP2P solves the scalability issue of P2P by setting up on-demand communication-specific links between cores. So, the occupied area and the total power consumption of communication architecture can be reduced significantly. We designed an on-chip self-reconfiguration core, c(2)PCAP so as to achieve DRP2P interconnects as fast as possible. The c(2)PCAP core is designed for Xilinx FPGAs and can partially reconfigure the FPGA at the highest rate proposed by the manufacturer (e.g. up to 400 MB/s for Virtex-4). (C) 2012 Elsevier B.V. All rights reserved.