FPGA implementation of Radix-2(2) Pipelined FFT Processor

Saeed A., Elbably M., Abdelfadeel G., Eladawy M. I.

8th WSEAS Int Conference on Signal Processing/3rd WSEAS Int Symposium on Wavelets Theory and Applicat in Appl Math, Signal Proc and Modern Sci, İstanbul, Türkiye, 30 Mayıs - 01 Haziran 2009, ss.109-111 identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Basıldığı Şehir: İstanbul
  • Basıldığı Ülke: Türkiye
  • Sayfa Sayıları: ss.109-111


The Fast Fourier Transform (FFT) is very important algorithm in signal processing, software-defined radio, and wireless communication. This paper explains the realization of radix-2(2) single-path delay feedback pipelined FFT processor. This architecture has the same multiplicative complexity as radix-4 algorithm, but retains the simple butterfly structure of radix-2 algorithm. The implementation was made oil a Field Programmable Gate Array (FPGA) because it call achieve higher computing speed than digital signal processors (DSPs), and also can achieve cost effectively ASIC-like performance with lower development time, and risks. The processor has been developed using hardware description language VHDL and simulated up to 465 MHz on an Xilinx xc5vsx35t for transformation length 256-point.