Towards efficient hardware acceleration on Zynq Ultrascale+ MPSoC based Kria KV260 FPGA board for ADAS: A hybrid co-design approach for real-time computing
Integration, cilt.112, 2027 (SCI-Expanded, Scopus)
- Yayın Türü: Makale / Tam Makale
- Cilt numarası: 112
- Basım Tarihi: 2027
- Doi Numarası: 10.1016/j.vlsi.2026.102899
- Dergi Adı: Integration
- Derginin Tarandığı İndeksler: Science Citation Index Expanded (SCI-EXPANDED), Scopus, Applied Science & Technology Source, Compendex, INSPEC, zbMATH, Academic Search Ultimate (EBSCO), Engineering Source (EBSCO)
- Anahtar Kelimeler: Advanced driver assistance systems, Deep processing unit, Embedded systems, Hardware accelerator, Hardware–software co-design, Multi-task learning, Real-time computing, ZYNQ UltraScale+ MPSoC
- Marmara Üniversitesi Adresli: Evet
Özet
This paper presents a novel hw-sw co-design framework for multi-task learning (MTL) on the Zynq UltraScale+ MPSoC, enabling simultaneous object detection and semantic segmentation with minimal computational overhead. Unlike prior works that address either algorithmic optimization or hardware acceleration in isolation, the proposed method integrates model-level quantization-aware training (QAT) with platform-specific dataflow and memory mapping optimizations, ensuring balanced workload distribution between the Processing System (PS) and Programmable Logic (PL). The system utilizes a shared ResNet-18 backbone and an SSD-based detection head, optimized for INT8 inference on the Kria KV260 platform, utilizing the B3136 Deep Processing Unit (DPU) architecture. Performance is validated on large-scale datasets under diverse real-world driving conditions. Results demonstrate real-time throughput of 47.5 FPS, power consumption of only 6.95 W, and improved accuracy (mAP: 51.7%, mIoU: 59.65%) without significant degradation from FP32 baselines. Compared to state-of-the-art embedded vision systems, the proposed approach achieves a superior performance–efficiency trade-off, with up to 26.3% lower hardware resource usage and a higher composite performance evaluation index (PEI). These findings highlight the scalability and adaptability of the design, making it a promising candidate for next-generation ADAS platforms where low power, high throughput, and multi-task capability are critical.