Synthesizable Time Measurement and Test Scheme for SoC Architecture

Abas M. A.

8th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics, İstanbul, Türkiye, 30 Mayıs - 01 Haziran 2009, ss.25-31 identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Basıldığı Şehir: İstanbul
  • Basıldığı Ülke: Türkiye
  • Sayfa Sayıları: ss.25-31
  • Marmara Üniversitesi Adresli: Hayır

Özet

This paper presents a Synthesizable high-resolution time measurement and test scheme for digital System on Chip (SoC) application namely Two-Delay Interpolation Method (TDIM). The scheme is designed to measure internal timing parameters in SoC architecture such as jitter, set-zip and hold lime, delay faults and etc. Simulation result shows the circuit is capable to measure as low as 5 ps timing interval and the range Of measurement is programmable using programmable logic core in SoC. The small size of the design makes it eminently suitable for SoC applications, particularly when the accurate measurement Of small lime intervals are required; a need which is increasing as operational speeds tend toward 100GHz.