Akademik Veri Yönetim Sistemi
Proc. of the International Conference on Electrical, Computer and Energy Technologies (ICECET), Cape-Town, Güney Afrika, 9 - 10 Aralık 2021, ss.1-5
A high-speed rail-to-rail CMOS buffer amplifier with LCD column driver application and a very simple circuit structure, is proposed. The buffer employs a differential FVF at the input stage as a main circuit block as well as a smaller number of transistors compared to many other buffer designs. Advantages of this buffer compared to many others are low quiescent current, very small output impedance and a very small settling time characteristic. The main simulations have been performed using LTSpice with 0.35 mu m CMOS technology parameters, whereas the layout is drawn using Microwind. The simulations reveal a result of 0.3 mu s in terms of settling time with a power supply of 3.3 V while driving a 1 nF capacitive load and the quiescent current is found to be 3.95 mu A. The buffer amplifier is also analyzed in terms of FOM (Figure-of-Merit) performance measure and compared to other previous published buffers, in which the proposed circuit shows an outstanding and better performance. Moreover, the robustness of the proposed circuit to process mismatches and tolerances are verified by Monte Carlo analysis