On the convex formulation of area for slicing floorplans

Unutulmaz A., Dundar G., Fernandez F. V.

INTEGRATION-THE VLSI JOURNAL, cilt.50, ss.74-80, 2015 (SCI-Expanded) identifier identifier

  • Yayın Türü: Makale / Tam Makale
  • Cilt numarası: 50
  • Basım Tarihi: 2015
  • Doi Numarası: 10.1016/j.vlsi.2015.01.008
  • Dergi Adı: INTEGRATION-THE VLSI JOURNAL
  • Derginin Tarandığı İndeksler: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Sayfa Sayıları: ss.74-80
  • Anahtar Kelimeler: Layout for analog circuits, Slicing floorplan, Area optimization, Convexity of area
  • Marmara Üniversitesi Adresli: Hayır

Özet

In this paper, it is shown that the area optimization problem of a compact slicing floorplan may be formulated as a convex optimization problem when the areas of the analog components are modeled with continuous convex functions of the width (height). It is proved that the area of a compact slicing floorplan is a convex function of its width (height). The convexity is shown for the cases with and without dead (empty) space. This feature can be exploited to efficiently optimize the dimensions of layout components with multiple variants, without enumerating all possible combinations. Layout of a voltage-doubler circuit is used to quantitatively verify the proof. (C) 2015 Elsevier BM. All rights reserved.