Reliability-aware core partitioning in chip multiprocessors

Oz I., TOPCUOĞLU H. R. , Kandemir M., Tosun O.

JOURNAL OF SYSTEMS ARCHITECTURE, vol.58, pp.160-176, 2012 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 58
  • Publication Date: 2012
  • Doi Number: 10.1016/j.sysarc.2012.02.005
  • Page Numbers: pp.160-176


Executing multiple applications concurrently is an important way of utilizing the computational power provided by emerging chip multiprocessor (CMP) architectures. However, this multiprogramming brings a resource management and partitioning problem, for which one can find numerous examples in the literature. Most of the resource partitioning schemes proposed to date focus on performance or energy centric strategies. In contrast, this paper explores reliability-aware core partitioning strategies targeting CMPs. One of our schemes considers both performance and reliability objectives by maximizing a novel combined metric called the vulnerability-delay product (VDP). The vulnerability component in this metric is represented with Thread Vulnerability Factor (TVF), a recently proposed metric for quantifying thread vulnerability for multicores. Execution time of the given application represents the delay component of the VDP metric. As part of our experimental analysis, proposed core partitioning schemes are compared with respect to normalized weighted speedup, normalized weighted reliability loss and normalized weighted vulnerability delay product gain metrics for various workloads of benchmark applications. (C) 2012 Elsevier B.V. All rights reserved.