Performance and Energy Efficient Asymmetrically Reliable Caches for Multicore Architectures


Arslan S. , TOPCUOĞLU H. R. , Kandemir M. T. , Tosun O.

29th IEEE International Parallel and Distributed Processing Symposium (IPDPS), Hyderabad, Pakistan, 25 - 29 May 2015, pp.1025-1032 identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/ipdpsw.2015.113
  • City: Hyderabad
  • Country: Pakistan
  • Page Numbers: pp.1025-1032

Abstract

Modern architectures are increasingly susceptible to transient and permanent faults due to continuously decreasing transistor sizes and faster operating frequencies. The probability of soft error occurrence is relatively high on cache structures due to the large area of the logic compared to other parts. Applying fault tolerance unselectively for all caches has a significant overhead on performance and energy. In this study, we propose asymmetrically reliable caches aiming to provide required reliability using just enough extra hardware under the performance and energy constraints. In our framework, a chip multiprocessor consists of one reliability-aware core which has ECC protection on its data cache for critical data and a set of less reliable cores with unprotected data caches to map non-critical data. The experimental results for selected applications show that our proposed technique provides 21% better reliability for only 6% more energy consumption compared to traditional caches.