Akademik Veri Yönetim Sistemi
IEEE Access, cilt.13, ss.156486-156496, 2025 (SCI-Expanded)
Binary logic based FPGAs have been successfully used in a wide range of applications. Although these devices offer clear advantages, their programmable routing requires significant wiring resources between logic blocks. This overhead can be mitigated by employing multiple-valued logic instead of binary logic for signal transmission. Hence, multiple-valued FPGAs emerged. These devices are based on multiple-valued look-up tables and flip-flops within their configurable logic blocks. Although this is a valid strategy, it needs separate combinational and sequential elements which result in high power consumption. To overcome this problem, we propose a novel T-gate based architecture. Our architecture has the advantage of merging the look-up table and flip-flops within multiple-valued logic based configurable logic blocks. The proposed architecture is general such that it is applicable to any multiple-valued logic level and results in significant reduction in power consumption. Moreover, the proposed architecture significantly improves robustness against process variations. We compare the proposed architecture against recent studies to evaluate its performance. We show its strengths and weaknesses this way. All simulation files for the proposed architecture are made publicly available in our GitHub repository [https://github.com/ahmetunu/Nary-LUT/]. Hence, the readers can test and extend them in future studies.