Compiler-Enhanced Reliability for Network-on-Chip Architectures

Sasongko M. A. , TOPCUOĞLU H. R. , Arslan S. , Kandemir M. T.

25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), St Petersburg, Russia, 6 - 08 March 2017, pp.584-588 identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/pdp.2017.102
  • City: St Petersburg
  • Country: Russia
  • Page Numbers: pp.584-588


The small feature sizes in current Networks-on-chip (NoCs) have increased the importance of reliability. However, existing fault tolerance schemes incur costs in terms of performance and power consumption which can be over-burdening. In order to tackle the reliability problem in NoCs while minimizing the performance and energy costs, a compiler-enhanced reliability scheme is introduced in this paper which assigns extra protection only to data transmissions in NoC which are considered critical. The experimental study validates that our scheme yields almost equal level of fault tolerance for critical data transmissions with the scheme that protects all packet transmissions indiscriminately. Our scheme is also shown to have better performance by approximately 7% than the conservative scheme for the tested criticality annotation.